Digital logic design by brian holdsworth pdf

  1. Digital Logic Design, 4th Edition
  2. Digital Logic Design by Brian Holdsworth and Clive Woods - Read Online
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  4. Digital Logic Design

Digital Logic Design, 4th Edition. 1 review. by Clive Woods, Brian Holdsworth. Publisher: Newnes. Release Date: November ISBN: Preface to the fourth edition In this newly revised edition of DigitalLogicDesign, we have taken the opportunity to undertake extensive revisions. This books (Digital Logic Design [PDF]) Made by BRIAN HOLDSWORTH About Books A To Download Please Click.

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Digital Logic Design By Brian Holdsworth Pdf

Digital Logic Design, Fourth Edition Brian Holdsworth, Clive Woods books to read online, online library, greatbooks to read, PDF best books to read, top books . Digital Logic Design - 4th Edition - ISBN: , Authors: Brian Holdsworth Clive Woods DRM-free (EPub, PDF, Mobi). × DRM- . Clive Woods and the staff at Newnes would like to dedicate this book to the memory of Brian Holdsworth, who wrote the first edition of Digital Logic Design for.

New, updated and expanded topics in the fourth edition include: The section on fault-finding has been expanded. A new chapter is dedicated to the interface between digital components and analog voltages. Brian was closely involved in the preparation of this fourth edition and died shortly before its publication. The right of Brian Holdsworth and Clive Woods to be identified as the authors of this work has been asserted in accordance with the Copyright, Designs and Patents Act No part of this publication may be reproduced in any material form including photocopying or storing in any medium by electronic means and whether or not transiently or incidentally to some other use of this publication without the written permission of the copyright holder except in accordance with the provisions of the Copyright, Designs and Patents Act or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London, England W1T 4LP. In this newly revised edition of Digital Logic Design , we have taken the opportunity to undertake extensive revisions of much material contained in the third edition, whilst retaining its comprehensive coverage of the subject. To this end, we have retained all elementary material assuming little or no background, but the advanced chapters have accordingly been revised to take account of recent trends in hardware availability. The chapter on instrumentation and interfacing is almost entirely new, and the chapters on programmable logic devices, and on fault diagnosis and testing, have been considerably enlarged as a result, on the one hand, of significant advances in the technology and the range of devices now available to the designer, and on the other hand to emphasise that logical fault-finding methods, far from being esoteric, impossible to apply in practice, trivial, or demeaning for a professional engineer to use, are actually worthy of serious study and application. Material enclosed in boxes in this manner is usually not needed later in this text, and is not as important as the main narrative, or sometimes summarises work in the main text. This material may be rather more demanding than the main text, or be unusual or obscure in some other manner; generally speaking, proofs of results in these sections and subsections are not given in detail, and are left as more of a challenge for the interested reader to work out in full.

The com- plement is only taken in the case of negative numbers. Examples of 8-bit numbers in the l's complement representation follow: For these reasons the 2's complement represen- tation is generally preferred for numerical computations in a digital machine.

The table in Figure 1. For positive numbers the sign bit is 1 and for negative numbers it is 0. In the four representations described, with the exception of offset binary, positive numbers remain unchanged when signed. Subtrahends are regarded as negative numbers and are converted to their 2's complement form. They are then added to the positive minuend. When adding two negative numbers they are both converted to their 2's complement form before addition takes place.

Six possible cases are considered for the addition and subtraction of two 8-bit numbers where the MSB represents the sign digit and is given a negative weighting of The incorrect answer is obtained because the sum, , cannot be represented by seven binary digits and arithmetic overflow has occurred from the magnitude section into the position occupied by the sign digit. Subtrahend in 2's complement form. Difference found by addition. If the working registers happen to be 8-bits wide the carry out is auto- matically lost.

It will be observed that the numerical value of the subtrahend can be obtained directly from its 2's complement representation by including the negative weighting of the sign digit in the numerical evaluation. True magnitude is found by taking the 2's complement of the sum as shown below. Both numbers are expressed in 2's complement form. A carry is generated out of the sign bit position which has to be discarded. As in the previous case the magnitude is found by taking the 2's complement of the sum.

The correct answer cannot be represented by seven binary digits. Figure 1. It will be recalled that 2 n -- X has previously been defined as the 2's complement of X and it dd44 11C I00 Number systems and codes 13 follows that a correct answer is obtained by adding the 2's complement of the subtrahend to the minuend.

Subtrahend in l's complement form. Both numbers expressed in l's complement form. Multiplicand Multiplier Figure 1. A set of rules for the process of multiplication can be stated as follows: If the least significant bit LSB of the multiplier is 1 write down the multiplicand and shift one place left. If the LSB of the multiplier is 0 write down a number of 0s equal to the number of bits in the multiplicand and shift one place left. For each bit of the multiplier repeat either 1 or 2.

Add all the partial products to form the final product. Such a set of rules is called an algorithm which the digital designer can, if required, implement in hardware. In practice, the hardware implementation of the multiplication of unsigned numbers differs from the pencil and paper method in one important aspect.

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The partial products are accumulated as they are generated rather than all being added together at the end. An example of the shift and add technique is given below: Add MD 11 13 1. Providing the multiplicand and the multiplier are both positive, the shift and add process is valid.

Number systems and codes 15 However, assuming that the multiplier or the multiplicand, or both, are negative, 2's complement arithmetic must be employed. The introduction of the sign digits and the use of the 2's complement form for negative numbers introduces a number of complications. Correction factors are required for certain cases and the required correc- tion methods lead to complicated logic correction circuits.

An alternative and more elegant method is due to A D Booth.

Digital Logic Design, 4th Edition

With this scheme the procedure is the same regardless of signs. The method is beyond the scope of this introductory treatment of number systems and the reader is recommended to consult Lewin see bibliography. Complement arithmetic is used so that the subtraction operation becomes an addition.

This is illustrated in the following two examples which cover the two conditions described previously. The division process can be regarded as one of repeated subtraction of the divisor X from the dividend Y. The division equation may be written as: When the divisor is to be subtracted from the dividend or a partial remainder, there are only two possibilities.

Either it will subtract and a positive result is obtained or it will This leads to the restoring division process illustrated in the following example: Align the most significant bits of the divisor and dividend. Add the 2's complement of the divisor to the dividend. If the most significant digit is 1 and Co- 0 the answer is negative.

Restore the dividend, shift it left and record the quotient bit Q -- Co If the most significant digit is 0 and Co - 1, the answer is positive, the subtraction is valid. Repeat 2 , 3 , and 4 until the least significant digits of the dividend and divisor are aligned.

They are the fixed point and floating point systems. In practice, in a fixed point system, binary numbers are expressed as fractions with the radix point positioned Number systems and codes 17 immediately right of the sign digit. For example, in a machine using 8-bit registers Unfortunately there are problems associated with fixed point arithmetic. Assuming 8-bit registers are being used in the machine, the range of the registers has been exceeded.

The same problem exists for the multiplication and division operations. If two 8-bit numbers are multiplied, one by the other, then in many cases a double- length product will be formed and this would require a bit register.

Similarly, for the division operations, a fractional quotient can only be formed if the divisor is greater than the dividend. To overcome the range problems experienced with fixed point representation a floating point system can be used. Numbers in this system are expressed in the following form: When performing a computation, a normalised form of the mantissa is used.

Normalisation is achieved by adjusting the exponent so that the mantissa has a 1 in its most significant digit position. When this condition is satisfied: The principle of a biased exponent is perhaps more easily understood using the decimal system. Consider the following two decimal numbers: As a result at the interface between a digital device and the outside world facilities must be provided to convert pure binary to a decimal representation.

In practice, for example, calculators have been designed to work entirely in a decimal mode. In such cases decimal digits are represented by a string of binary digits referred to as a code. Four bits are required to represent the ten decimal digits, and since there are 24 combinations of four binary digits, six combinations are not used and the code is said to contain redundancy.

The four binary digits can be allocated to ten decimal digits in a purely arbitrary manner and it is possible to generate 2. The most common group of codes for representing decimal numbers are weighted and there are 17 of these codes.

Of this group the most commonly used weighted code is naturally binary coded decimal NBCD which uses the first ten combinations of the 4-bit binary count from to inclusive. The code weighting for NBCD is 8, 4, 2, 1 and this can be used to find the corresponding decimal value of a given code.

Such a code is the 8, 4, -2,-1 which, like the 2, 4, 2, 1 code, has the useful property of self-complementation. By complementing each of the bits of a given codeword, a new codeword is formed which represents the 9's complement of the decimal digit represented by the original codeword. Another example of a self-complementing code is the XS3 code.

Digital Logic Design by Brian Holdsworth and Clive Woods - Read Online

This is not a weighted code but contains combinations of natural binary in the range 3 10 to 12 The decimal value allocated to each binary code is defined to be 3 less than its actual value. For example, 1 10 is represented by Decimal digit 0 1 2 3 4 5 6 7 8 9 NBCD 8,4,2,1 BCD 7,4,2,1 BCD BCD 2,4,2,1 8,4,-2,-1 Figure 1.

Number systems and codes 19 Decimal digit Biquinary 2-out-of 5 0 1 2 3 4 5 O0 6 7 1O O0 8 O0 1O 9 Figure 1. Two examples of these are the 2-out-of-5 code and the biquinary code both of which are tabulated in Figure 1. It will be observed that each codeword in the 2-out-of-5 tabulation contains two l's and a single error that complements one of the bits will generate an invalid code.

The biquinary code is a weighted code where seven binary digits represent each of the decimal digits. The two most significant bits in each codeword, 01 and 10 indicate whether the digit represented is in the range 0 10 to 4 10 or 5 10 to 9 10 respectively. Each code combination contains only two l's and the complementation of a single bit in a code- word will generate an invalid code. Examples of 1, 2, and 3-cubes are illustrated in Figure 1.

It will be observed from these diagrams that there is a single bit difference between the binary strings positioned at adjacent vertices. The distance between any two vertices on an n-cube is defined as the number of bit positions in which the two binary strings differ. Alternatively this is called the Hamming distance.

A pair of adjacent vertices labelled and are a distance of 1 apart while the two binary strings and are a distance 2 apart. A more formal approach to the concept of distance follows: The modulo-2 sum of two binary digits is given in the four following equations: The weight of a codeword g is defined as the number of l's contained in the word. To improve the reliability of the system, methods are used to indicate the occurrence of an error and in some systems arrangements are made for both the detection and correction of errors.

A single-bit error occurs when a 0 is converted to a 1 or vice versa. Multiple errors may also occur, but it is normally assumed that these are less likely to occur than single-bit errors. The practical way of reducing error probability in a digital system is to introduce a controlled amount of redundancy.

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The 2-out-of-5 code is a typical example of such a code. In all, there are 25 combinations of five bits of which only ten are used, the remaining twenty two combinations being redundant.

The ten combinations used, are the only combinations which contain two l's and are tabulated in Figure 1. Any odd number of errors in a specified codeword will result in the received word having an odd number of l's.

Double or quadruple errors will also be detected unless a 1 is com- pensated by an error in a 0, thus ensuring the received codeword still contains two l's.

The concept of distance is crucial in the design and understanding of error detecting codes. All single-bit errors will be detected if there is a minimum distance of 2 between all possible pairs of codewords.

A minimum distance of 2 can be achieved by adding an extra bit to the transmitted word. This additional bit is called a parity bit.

Digital Logic Design

Two different parity systems are currently in use. In an even parity system the parity bit to be added to the codeword is chosen so that the number of l's in the modified word is even, whilst in the oddparity system the added bit is chosen so that the number of l's in the modified word is odd. A 3-bit code is tabulated in Figure 1. It will be observed from this tabulation that a minimum distance of 2 is maintained between all adjacent pairs of modified codewords.

Number systems and codes 21 Modified Code Original Code Even Odd parity parity 1O0 1O01 Figure 1. The technique is termed iterativeparity checking. An array formed from 4-bit words is shown in Figure 1.

Parity bits providing even parity are attached to each row and column. After attachment of the parity bits, the array shown in Figure 1. A single-bit error in this array can be both detected and corrected. The method allows the position in the array where the error has occurred to be identified and correction can then take place. The error detection and correction procedure for the array consists, first, of checking the row parities and that reveals that there is an error in the top row of the array.

At this point in the procedure it is not possible to determine which bit in the row is in error. However if a bit-by-bit XOR is taken of all the words in the array excepting the row in error but including the column check row the column in error is identified and the error corrected. The bit positions in the codeword are numbered from 1 to 2r - 1 and any position in the codeword whose number is a power of 2 contains a parity bit. For a 7-bit codeword the parity bits occupy positions 1, 2 and 4 so that the format of the transmitted codeword is" bit position 7, 6, 5, 4, 3, 2, 1 C -- k4k3k2r3klr2rl The bit positions occupied by the parity bits 4, 2 and 1 when converted to binary are , and Each of these conversions contains a single 1 and are grouped with message bits k4k3kEkl whose numbers contain a 1 in the same bit position.

For example, rl in bit position is grouped with message bits that occupy the bit positions 3 , l01 5 and 7. It is then arranged that for a given combination of message bits the parity bit is allocated so that even parity is achieved. The value of parity bit rl is given by XORing the message bits in bit positions 7, 5 and 3. For this message the parity check bits to be transmitted with the message bits are: In terms of distance, a Gray code is a unit distance code.

One particular form of Gray code is called reflected binary, which can be constructed using the following technique. The two binary digits 0 and 1 are reflected about a horizontal line and the digits above the line are prefixed by 0 and below the line by 1 as shown below: This process can now be extended by reflecting the four 2-bit combinations placed below the combination 10 and Reflected binary Natural binary Figure 1.

The eight 3-bit combinations generated are tabulated in Figure 1. An alternative method of translating from the binary number system to the Gray code tabulated in Figure 1. Thus the Gray code corresponding to in binary is generated as follows: If the two changes do not coincide, then transient states of or may occur. This generation of transient states is of significance in the design of angular digital encoders which are used to measure the angular position of a rotating shaft.

The encoder disc shown in Figure 1. We would like to ask you for a moment of your time to fill in a short questionnaire, at the end of your visit.

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